A synchronous bus is a bus that has a clock and all signals on the bus are switched based on this clock. Both busses employed in embodiments of the present invention are synchronous since they both have a clock. However they are asynchronous to each other since there is no relationship between the two clocks.
There are many synchronization systems allowing different busses to access a RAM. They all start from the assumption that the relative speed of the busses is known. Some methods are suggested to synchronize a signal A to a signal B, e.g., if one knows A is at least 3 times faster than B. Other methods are used if A is at least 3 times slower than B.
In the implementation of such systems one often encounters master/slave situations: the master is writing data or code to the RAM (depending on the application) and the slave is executing the code or using the data.
The alternative solution is to use a dual port RAM, with bus A signals simply connected to port A of the RAM and bus B signals to port B of the RAM. This approach is disadvantageous in the number of gates it takes, namely twice the size of a single port RAM.